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M29W800DT45ZE6E 参数 Datasheet PDF下载

M29W800DT45ZE6E图片预览
型号: M29W800DT45ZE6E
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 1兆位×8或512千位×16 ,引导块) 3 V电源快闪记忆体 [8-Mbit (1 Mbit x 8 or 512 Kbits x 16, boot block) 3 V supply flash memory]
分类和应用:
文件页数/大小: 52 页 / 1105 K
品牌: NUMONYX [ NUMONYX B.V ]
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Description  
M29W800DT, M29W800DB  
1
Description  
The M29W800D is a 8-Mbit (1 Mbit x 8 or 512 Kbits x 16) non-volatile memory that can be  
read, erased and reprogrammed. These operations can be performed using a single low  
voltage (2.7 to 3.6 V) supply. On power-up the memory defaults to its read mode where it  
can be read in the same way as a ROM or EPROM.  
The memory is divided into blocks that can be erased independently so it is possible to  
preserve valid data while old data is erased. Each block can be protected independently to  
prevent accidental program or erase commands from modifying the memory. Program and  
erase commands are written to the command interface of the memory. An on-chip  
program/erase controller simplifies the process of programming or erasing the memory by  
taking care of all of the special operations that are required to update the memory contents.  
The end of a program or erase operation can be detected and any error conditions  
identified. The command set required to control the memory is consistent with JEDEC  
standards.  
The blocks in the memory are asymmetrically arranged, see Figure 5: Block addresses (x 8)  
and Figure 6: Block addresses (x 16). The first or last 64 Kbytes have been divided into four  
additional blocks. The 16-Kbyte boot block can be used for small initialization code to start  
the microprocessor, the two 8-Kbyte parameter blocks can be used for parameter storage  
and the remaining 32-Kbyte is a small main block where the application may be stored.  
Chip Enable, Output Enable and Write Enable signals control the bus operation of the  
memory. They allow simple connection to most microprocessors, often without additional  
logic.  
The memory is offered in SO44, TSOP48 (12 x 20 mm) and TFBGA48 6 x 8 mm (0.8 mm  
pitch) packages. The memory is supplied with all the bits erased (set to ’1’).  
Figure 1.  
Logic diagram  
V
CC  
19  
15  
A0-A18  
DQ0-DQ14  
DQ15A–1  
W
E
M29W800DT  
M29W800DB  
G
RB  
RP  
BYTE  
V
SS  
AI05470B  
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