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M29W800DT45ZE6E 参数 Datasheet PDF下载

M29W800DT45ZE6E图片预览
型号: M29W800DT45ZE6E
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 1兆位×8或512千位×16 ,引导块) 3 V电源快闪记忆体 [8-Mbit (1 Mbit x 8 or 512 Kbits x 16, boot block) 3 V supply flash memory]
分类和应用:
文件页数/大小: 52 页 / 1105 K
品牌: NUMONYX [ NUMONYX B.V ]
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Status register  
M29W800DT, M29W800DB  
5.3  
Error bit (DQ5)  
The error bit can be used to identify errors detected by the program/erase controller. The  
error bit is set to ’1’ when a program, block erase or chip erase operation fails to write the  
correct data to the memory. If the error bit is set a Read/Reset command must be issued  
before other commands are issued. The error bit is output on DQ5 when the status register  
is read.  
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to  
do so will set DQ5 to ‘1’. A bus read operation to that address will show the bit is still ‘0’. One  
of the erase commands must be used to set all the bits in a block or in the whole memory  
from ’0’ to ’1’  
5.4  
5.5  
Erase timer bit (DQ3)  
The erase timer bit can be used to identify the start of program/erase controller operation  
during a Block Erase command. Once the program/erase controller starts erasing the erase  
timer bit is set to ’1’. Before the program/erase controller starts the erase timer bit is set to ’0’  
and additional blocks to be erased may be written to the command interface. The erase  
timer bit is output on DQ3 when the status register is read.  
Alternative toggle bit (DQ2)  
The alternative toggle bit can be used to monitor the program/erase controller during erase  
operations. The alternative toggle bit is output on DQ2 when the status register is read.  
During chip erase and block erase operations the toggle bit changes from ’0’ to ’1’ to ’0’,  
etc., with successive bus read operations from addresses within the blocks being erased. A  
protected block is treated the same as a block not being erased. Once the operation  
completes the memory returns to read mode.  
During erase suspend the alternative toggle bit changes from ’0’ to ’1’ to ’0’, etc. with  
successive bus read operations from addresses within the blocks being erased. Bus read  
operations to addresses within blocks not being erased will output the memory cell data as if  
in read mode.  
After an erase operation that causes the error bit to be set the alternative toggle bit can be  
used to identify which block or blocks have caused the error. The alternative toggle bit  
changes from ’0’ to ’1’ to ’0’, etc. with successive bus read operations from addresses within  
blocks that have not erased correctly. The alternative toggle bit does not change if the  
addressed block has erased correctly.  
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