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M29W640GT90NA6F 参数 Datasheet PDF下载

M29W640GT90NA6F图片预览
型号: M29W640GT90NA6F
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(8MB X8或X16 4Mb的,页) 3V供应闪存 [64 Mbit (8Mb x8 or 4Mb x16, Page) 3V supply Flash memory]
分类和应用: 闪存存储内存集成电路光电二极管ISM频段
文件页数/大小: 90 页 / 1676 K
品牌: NUMONYX [ NUMONYX B.V ]
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Command Interface  
M29W640GH, M29W640GL, M29W640GT, M29W640GB  
4.2  
Fast Program commands  
There are five Fast Program commands available to improve the programming throughput,  
by writing several adjacent words or bytes in parallel:  
Quadruple and Octuple Byte Program, available for x8 operations  
Double and Quadruple Word Program, available for x16 operations  
Write to Buffer and Program  
Fast Program commands can be suspended and then resumed by issuing a Program  
Suspend command and a Program Resume command, respectively (see Section 4.1.8:  
Program Suspend command and Section 4.1.9: Program Resume command).  
4.2.1  
Double Byte Program command  
The Double Byte Program command is used to write a page of two adjacent bytes in  
parallel. The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to  
issue the Double Byte Program command.  
1. The first bus cycle sets up the Double Byte Program Command.  
2. The second bus cycle latches the Address and the Data of the first byte to be written.  
3. The third bus cycle latches the Address and the Data of the second byte to be written.  
Note:  
It is not necessary to raise V /WP to 12V before issuing this command.  
PP  
4.2.2  
Quadruple Byte Program command  
The Quadruple Byte Program command is used to write a page of four adjacent bytes in  
parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles  
are necessary to issue the Quadruple Byte Program command:  
1. The first bus cycle sets up the Quadruple Byte Program Command.  
2. The second bus cycle latches the Address and the Data of the first byte to be written.  
3. The third bus cycle latches the Address and the Data of the second byte to be written.  
4. The fourth bus cycle latches the Address and the Data of the third byte to be written.  
5. The fifth bus cycle latches the Address and the Data of the fourth byte to be written and  
starts the Program/Erase Controller.  
Note:  
It is not necessary to raise V /WP to 12V before issuing this command.  
PP  
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