M29W640GH, M29W640GL, M29W640GT, M29W640GB
Bus operations
3
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Table 7: Bus Operations, BYTE
= V and Table 8: Bus Operations, BYTE = V , for a summary. Typically glitches of less
IL
IH
than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
3.1
3.2
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V , to Chip Enable and Output Enable and keeping Write
Enable High, V . The Data Inputs/Outputs will output the value, see Figure 13: Read Mode
ac waveforms (8-bit mode), and Table 18: Read ac characteristics, for details of when the
IL
IH
output becomes valid.
Bus Write
Bus Write operations write to the Command Interface. To speed up the read operation the
memory array can be read in Page mode where data is internally read and stored in a page
buffer. The Page has a size of 4 words and is addressed by the address inputs A0-A1.
A valid Bus Write operation begins by setting the desired address on the Address Inputs.
The Address Inputs are latched by the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, V , during the whole Bus Write operation. See
IH
Figure 15: Write ac waveforms, Write Enable Controlled (8-bit mode), Figure 16: Write ac
waveforms, Chip Enable Controlled (8-bit mode), and Table 19: Write ac characteristics and
Table 19: Write ac characteristics, for details of the timing requirements.
3.3
3.4
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V .
IH
Standby
When Chip Enable is High, V , the memory enters Standby mode and the Data
IH
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
, Chip Enable should be held within V
0.2V. For the
CC2
CC
Standby current level see Table 17: DC characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I , for Program or Erase operations until the operation completes.
CC3
19/90
NUMONYX [ NUMONYX B.V ]
