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M29W400DT70ZA1 参数 Datasheet PDF下载

M29W400DT70ZA1图片预览
型号: M29W400DT70ZA1
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512 KB ×8或256 KB ×16 ,引导块) 3 V电源闪存 [4 Mbit (512 Kb x 8 or 256 Kb x 16, boot block) 3 V supply Flash memory]
分类和应用: 闪存
文件页数/大小: 48 页 / 1025 K
品牌: NUMONYX [ NUMONYX B.V ]
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Status Register  
M29W400DT, M29W400DB  
5
Status Register  
Bus Read operations from any address always read the Status Register during Program and  
Erase operations. It is also read during Erase Suspend when an address within a block  
being erased is accessed.  
The bits in the Status Register are summarized in Table 7: Status Register bits.  
5.1  
Data Polling bit (DQ7)  
The Data Polling bit can be used to identify whether the Program/Erase controller has  
successfully completed its operation or if it has responded to an Erase Suspend. The Data  
Polling bit is output on DQ7 when the Status Register is read.  
During Program operations the Data Polling bit outputs the complement of the bit being  
programmed to DQ7. After successful completion of the Program operation the memory  
returns to Read mode and Bus Read operations from the address just programmed output  
DQ7, not its complement.  
During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state  
of DQ7. After successful completion of the Erase operation the memory returns to Read  
mode.  
In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation  
within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the  
Program/Erase controller has suspended the Erase operation.  
Figure 7: Data polling flowchart, gives an example of how to use the Data Polling bit. A valid  
address is the address being programmed or an address within the block being erased.  
5.2  
Toggle bit (DQ6)  
The Toggle bit can be used to identify whether the Program/Erase controller has  
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle  
bit is output on DQ6 when the Status Register is read.  
During Program and Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with  
successive Bus Read operations at any address. After successful completion of the  
operation the memory returns to Read mode.  
During Erase Suspend mode the Toggle bit will output when addressing a cell within a block  
being erased. The Toggle bit will stop toggling when the Program/Erase controller has  
suspended the Erase operation.  
If any attempt is made to erase a protected block, the operation is aborted, no error is  
signalled and DQ6 toggles for approximately 100 µs. If any attempt is made to program a  
protected block or a suspended block, the operation is aborted, no error is signalled and  
DQ6 toggles for approximately 1 µs.  
Figure 8: Data toggle flowchart, gives an example of how to use the Data Toggle bit.  
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