M28W160CT, M28W160CB
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 2,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
state. When Reset is at V , the device is in normal
IH
operation. Exiting reset mode the device enters
read array mode, but a negative transition of Chip
Enable or a change of the address is required to
ensure valid data outputs.
V
Supply Voltage. V
provides the power
DD
DD
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
Supply Voltage. V
provides the
power supply to the I/O pins and enables all Out-
puts to be powered independently from V . V
DDQ
DDQ
DD DDQ
can be tied to V or can use a separate supply.
DD
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
V
Program Supply Voltage. V
is both a
PP
PP
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin. The Supply Voltage V and the
DD
Program Supply Voltage V
any order.
at V and Reset is at V the device is in active
IL
IH
mode. When Chip Enable is at V the memory is
can be applied in
PP
IH
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
If V is kept in a low voltage range (0V to 3.6V)
PP
V
is seen as a control input. In this case a volt-
PP
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable, E, or Write En-
able, W, whichever occurs first.
age lower than V
gives an absolute protection
PPLK
against program or erase, while V > V
en-
PP1
PP
ables these functions (see Table 15, DC Charac-
teristics for the relevant values). V is only
PP
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase op-
erations continue.
If V is in the range 11.4V to 12.6V it acts as a
PP
Write Protect (WP). Write Protect is an input
power supply pin. In this condition V must be
PP
that gives an additional hardware protection for
stable until the Program/Erase algorithm is com-
each block. When Write Protect is at V , the Lock-
IL
pleted (see Table 17 and 18).
Down is enabled and the protection status of the
block cannot be changed. When Write Protect is at
V
Ground. V is the reference for all voltage
SS
SS
V , the Lock-Down is disabled and the block can
measurements.
IH
be locked or unlocked. (refer to Table 7, Read Pro-
Note: Each device in a system should have
tection Register and Protection Register Lock).
V
, V
and V decoupled with a 0.1µF ca-
DD DDQ PP
Reset (RP). The Reset input provides a hard-
pacitor close to the pin. See Figure 8, AC Mea-
surement Load Circuit. The PCB trace widths
ware reset of the memory. When Reset is at V ,
IL
the memory is in reset mode: the outputs are high
impedance and the current consumption is mini-
mized. After Reset all blocks are in the Locked
should be sufficient to carry the required V
program and erase currents.
PP
9/50
NUMONYX [ NUMONYX B.V ]
