M25PX80
Figure 1.
Logic diagram
VCC
Description
DQ0
C
S
W/V
PP
HOLD
M25PX80
DQ1
VSS
AI14228
Table 1.
Signal names
Function
Serial Clock
Serial Data input
Serial Data output
Chip Select
Write Protect/Enhanced Program supply voltage
Hold
Supply voltage
Ground
Input
I/O
(1)
I/O
(2)
Input
Input
Input
Direction
Signal name
C
DQ0
DQ1
S
W/V
PP
HOLD
V
CC
V
SS
1. Serves as an output during Dual Output Fast Read (DOFR) instructions.
2. Serves as an input during Dual Input Fast Program (DIFP) instructions.
Figure 2.
VFQFPN, SO8, and PDIP8 connections
M25PX80
S 1
DQ1 2
W/V
PP
3
VSS 4
8
7
6
5
VCC
HOLD
C
DQ0
AI13720b
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
V
SS
, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See
Package mechanical
7/60
NUMONYX [ NUMONYX B.V ]
