M25PX64
Instructions
6.4.4
Top/bottom bit
The top/bottom (TB) bit is non-volatile. It can be set and reset with the write status register
(WRSR) instruction provided that the write enable (WREN) instruction has been issued. The
top/bottom (TB) bit is used in conjunction with the block protect (BP0, BP1, BP2) bits to
determine if the protected area defined by the block protect bits starts from the top or the
bottom of the memory array:
■
When top/bottom bit is reset to ‘0’ (default value), the area protected by the block
protect bits starts from the top of the memory array (see Table 3: Protected area sizes)
■
When top/bottom bit is set to ‘1’, the area protected by the block protect bits starts from
the bottom of the memory array (see Table 3: Protected area sizes).
The top/bottom bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven
Low.
6.4.5
SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the write protect
(W/V ) signal. The status register write disable (SRWD) bit and the write protect (W/V
)
PP
PP
signal allow the device to be put in the hardware protected mode (when the status register
write disable (SRWD) bit is set to ‘1’, and write protect (W/V ) is driven Low). In this mode,
PP
the non-volatile bits of the status register (SRWD, BP2, BP1, BP0) become read-only bits
and the write status register (WRSR) instruction is no longer accepted for execution.
Figure 11. Read status register (RDSR) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
DQ0
Status register out
Status register out
High Impedance
DQ1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
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NUMONYX [ NUMONYX B.V ]
