Instructions
M25PX64
6.8
Dual output fast read (DOFR)
The dual output fast read (DOFR) instruction is very similar to the read data bytes at higher
speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin DQ0
and pin DQ1) instead of only one. Outputting the data on two pins instead of one doubles
the data transfer bandwidth compared to the read data bytes at higher speed (FAST_READ)
instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the dual
output fast read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,
each bit being latched-in during the rising edge of Serial Clock (C). Then the memory
contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency f ,
C
during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 15.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole
memory can, therefore, be read with a single dual output fast read (DOFR) instruction.
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
Figure 15. Dual output fast read instruction sequence
S
Mode 3
Mode 2
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24-bit address (1)
DQ0
DQ1
23 22 21
3
2
1
0
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy byte
DQ0
DQ1
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DATA OUT 1 DATA OUT 2 DATA OUT 3
DATA OUT n
7
5
3
1
7
5
3
1
7
5
3
1
7
5
1
3
MSB
MSB
MSB
MSB
MSB
ai13574b
1. Address bit A23 is don’t care.
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NUMONYX [ NUMONYX B.V ]
