M25PX64
Figure 1.
Logic diagram
VCC
Description
DQ0
C
S
W/V
PP
HOLD
M25PX64
DQ1
VSS
AI14228b
Table 1.
Signal names
Function
Serial Clock
Serial Data input
Serial Data output
Chip Select
Write Protect/Enhanced Program supply voltage
Hold
Supply voltage
Ground
Input
I/O
(1)
I/O
(2)
Input
Input
Input
–
–
Direction
Signal name
C
DQ0
DQ1
S
W/V
PP
HOLD
V
CC
V
SS
1. Serves as an output during dual output fast read (DOFR) instructions.
2. Serves as an input during dual input fast program (DIFP) instructions.
Figure 2.
VDFPN8 connections
M25PX64
S
DQ1
W/V
PP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
DQ0
AI13720c
1. There is an exposed central pad on the underside of the VDFPN8 package. This is pulled, internally, to
V
SS
, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See
Package mechanical
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NUMONYX [ NUMONYX B.V ]
