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M25PX32 参数 Datasheet PDF下载

M25PX32图片预览
型号: M25PX32
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位,双I / O , 4 KB的界别分组擦除,串行闪存与75 MHz的SPI总线接口 [32-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 65 页 / 1324 K
品牌: NUMONYX [ NUMONYX B.V ]
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Operating features  
M25PX32  
4.5  
Fast Bulk Erase mode  
The Fast Bulk Erase mode is used to speed up Bulk Erase operations. The device enters  
the Fast Bulk Erase mode during a Bulk Erase instruction whenever a voltage equal to V  
PPH  
is applied to the W/V pin.  
PP  
The use of the Fast Bulk Erase mode requires specific operating conditions in addition to the  
normal ones (V must be within the normal operating range):  
CC  
the voltage applied to the W/V pin must be equal to V  
(see Table 13)  
PP  
PPH  
ambient temperature, T must be 25 °C ±10 °C,  
A
the cumulated time during which W/V is at V  
should be less than 80 hours.  
PPH  
PP  
4.6  
Active Power, Standby Power and Deep Power-down modes  
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.  
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power  
mode until all internal cycles have completed (Program, Erase, Write Status Register). The  
device then goes in to the Standby Power mode. The device consumption drops to I  
.
CC1  
The Deep Power-down mode is entered when the specific instruction (the Deep Power-  
down (DP) instruction) is executed. The device consumption drops further to I . The  
CC2  
device remains in this mode until another specific instruction (the Release from Deep  
Power-down (RDP) instruction) is executed.  
While in the Deep Power-down mode, the device ignores all Write, Program and Erase  
instructions (see Deep Power-down (DP)), this can be used as an extra software protection  
mechanism, when the device is not in active use, to protect the device from inadvertent  
Write, Program or Erase instructions.  
4.7  
Status Register  
The Status Register contains a number of status and control bits that can be read or set (as  
appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a  
detailed description of the Status Register bits.  
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