DC and AC parameters
M25PE80
(1)
Table 24.
Symbol
AC characteristics (75 MHz operation, T9HX (0.11 µm) process
Test conditions specified in Table 17 and Table 18
)
Alt.
Parameter
Min
Typ
Max
Unit
Clock frequency for the following instructions:
FAST_READ, RDLR, PW, PP, WRLR, PE, SE,
SSE, DP, RDP, WREN, WRDI, RDSR, WRSR
fC
fR
fC
D.C.
75
33
MHz
Clock frequency for read instructions
D.C.
6
MHz
ns
(2)
tCH
tCLH Clock high time
tCLL Clock low time
(2)
tCL
6
ns
Clock slew rate(2) (peak to peak)
0.1
5
V/ns
ns
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tCSS S active setup time (relative to C)
S not active hold time (relative to C)
tDSU Data in setup time
5
ns
2
ns
tDH
Data in hold time
5
ns
S active hold time (relative to C)
S not active setup time (relative to C)
5
ns
5
ns
tCSH S deselect time
100
ns
(3)
tSHQZ
tDIS Output disable time
8
ns
tCLQV
tCLQX
tV
Clock low to output valid under 30 pF/10 pF
8/6
ns
tHO
Output hold time
0
ns
(4)
tWHSL
Write protect setup time
Write protect hold time
20
ns
(4)
tSHWL
100
ns
(3)
tDP
S to deep power-down
3
µs
(3)
tRDP
S high to standby mode
Write status register cycle time
Page write cycle time (256 bytes)
Page program cycle time (256 bytes)
Page program cycle time (n bytes)
Page erase cycle time
30
15
23
µs
tW
3
ms
ms
(5)
tPW
11
0.8
(3)
tPP
3
ms
int(n/8) × 0.025(6)
tPE
tSE
tSSE
tBE
10
1
20
5
ms
s
Sector erase cycle time
Subsector erase cycle time
Bulk erase cycle time
50
10
150
20
ms
s
1. See Important note on page 6.
2. tCH + tCL must be greater than or equal to 1/ fC.
3. Value guaranteed by characterization, not 100% tested in production.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
5. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
6. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
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NUMONYX [ NUMONYX B.V ]
