M25PE80
Revision history
Table 32. Document revision history (continued)
Date
Version
Changes
Important note on page 6 added.
VFQFPN8 and SO8W packages updated and SO8N (MN) package
added (see Section 12: Package mechanical).
Figure 4: Bus master and memory devices on the SPI bus updated and
explanatory paragraph added.
Reset signal behavior specified in Section 6.8: Read lock register (RDLR),
Section 6.10: Page program (PP), Section 6.12: Page erase (PE) and
Section 6.14: Sector erase (SE) and Section 6.15: Bulk erase (BE).
Section 8: Reset added, Table 25: Reset conditions modified and
Table 26: Timings after a Reset Low pulse added.
Table 3: Not for new design: TY7 process only, software protection
scheme truth table (sectors 0 and 15) applies to T7Y process only.
Software protection scheme figure removed. B3 and b2 apply to T7Y
process only in Table 8: Status register format, Table 10: Lock registers
added, Table 11 applies to T7Y process only. Table 12: Lock register in
added, Table 13 applies to T7Y process only.
30-Nov-2006
5
Protection always prevails: applies to T7Y process only.
TLEAD added and VIO max changed in Table 16: Absolute maximum
ratings
M25PE80 products processed in T9HX process added to datasheet:
– WP pin replaces TSL (T7Y technology), see Section 2.6: Write protect
(W) or top sector lock (TSL)
– Write status register (WRSR) and Subsector erase (SSE) instructions
added for T9HX process
– subsector protection granularity removed in T9HX process, still exists in
T7Y process
– Table 5: Memory organization updated to show subsectors
– Status register BP2, BP1, BP0 bits and SRWD bit added.
SPM2 description and Table 4: Protected area sizes added in Section 4.8:
Protection modes.
15-Jan-2007
09-Apr-2008
6
7
VFQFPN8 package specifications updated (see Table 27 and Figure 30).
small text changes.
Removed ‘low voltage’ from the title.
Updated the value for the maximum clock frequency (from 50 to 75 MHz)
through the document.
Added: QFN8L package, Table 21: DC characteristics (75 MHz operation
(T9HX (0.11 µm process), Table 24: AC characteristics (75 MHz
operation, T9HX (0.11 µm) process), and ECOPACK® text in Section 12:
Package mechanical.
Modified: Table 20: DC characteristics, Table 4: Bus master and memory
devices on the SPI bus, and Section 6.3: Read identification (RDID).
Applied Numonyx branding.
65/66
NUMONYX [ NUMONYX B.V ]
