Instructions
M25PE40
6.8
Read Lock Register (RDLR)
Note:
The Read Lock Register (RDLR) instruction is decoded only in the M25PE40 in the T9HX
process (see Important note on page 6).
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector (or subsector). Each address bit is latched-in during
the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on
Serial Data output (Q), each bit being shifted out, at a maximum frequency f , during the
C
falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Table 9.
Bit
Lock Registers
Bit name
Value
Function
b7-b4
Reserved
The Write Lock and Lock Down bits cannot be changed. Once a
‘1’ is written to the Lock Down bit it cannot be cleared to ‘0’,
except by a reset or power-up.
‘1’
Sector Lock
Down
b1
The Write Lock and Lock Down bits can be changed by writing
new values to them (default value).
‘0’
‘1’
‘0’
Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
Sector Write
Lock
b0
Write, Program and Erase operations in this sector are executed
and will modify the sector contents (default value).
Figure 14. Read Lock Register (RDLR) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
23 22 21
MSB
3
2
1
0
D
Q
Lock Register Out
High Impedance
2
7
6
5
4
3
1
0
MSB
AI10783
30/62
NUMONYX [ NUMONYX B.V ]
