M25PE16
Power-up and power-down
7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V ) until V reaches the correct value:
CC
CC
■
■
V
V
(min) at power-up, and then for a further delay of t
at power-down
CC
SS
VSL
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while V is less than the
CC
power on reset (POR) threshold voltage, V – all operations are disabled, and the device
WI
does not respond to any instruction.
Moreover, the device ignores all write enable (WREN), page write (PW), page program (PP),
page erase (PE), sector erase (SE), subsector erase (SSE), bulk erase (BE), write status
register (WRSR) and write to lock register (WRLR) instructions until a time delay of t
PUW
has elapsed after the moment that V rises above the V threshold. However, the correct
CC
WI
operation of the device is not guaranteed if, by this time, V is still below V (min). No
CC
CC
write, program or erase instructions should be sent until the later of:
■
■
t
t
after V passed the V threshold
CC WI
PUW
VSL
after V passed the V (min) level
CC
CC
These values are specified in Table 11.
If the delay, t
, has elapsed, after V has risen above V (min), the device can be
VSL
CC
CC
selected for read instructions even if the t
delay is not yet fully elapsed.
PUW
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the power-up and power-down phases.
At power-up, the device is in the following state:
■
■
■
■
The device is in the standby mode (not the deep power-down mode).
The write enable latch (WEL) bit is reset.
The write in progress (WIP) bit is reset
The lock registers are reset (write lock bit, lock down bit) = (0, 0)
Normal precautions must be taken for supply rail decoupling, to stabilize the V supply.
CC
Each device in a system should have the V line decoupled by a suitable capacitor close to
CC
the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when V drops from the operating voltage, to below the power on reset
CC
(POR) threshold voltage, V , all operations are disabled and the device does not respond
WI
to any instruction. The designer needs to be aware that if a power-down occurs while a
write, program or erase cycle is in progress, some data corruption can result.
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NUMONYX [ NUMONYX B.V ]
