M25PE20, M25PE10
Reset
8
Reset
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
All the Lock bits are reset to ‘0’ after a Reset Low pulse.
Table 14 shows the status of the device after a Reset Low pulse.
Table 14. Device status after a Reset Low pulse
Conditions:
Reset pulse occurred
Internal logic
status
Lock bits status
Addressed data
While decoding an instruction(1): WREN,
WRDI, RDID, RDSR, READ, RDLR,
Fast_Read, WRLR, PW, PP, PE, SE, BE,
SSE, DP, RDP
Reset to ‘0’
Same as POR
Not significant
Under completion of an Erase or Program
cycle of a PW, PP, PE, SSE, SE, BE
operation
Equivalent to
POR
Addressed data
could be modified
Reset to ‘0’
Equivalent to Write is correctly
Under completion of a WRSR operation
Reset to ‘0’
Reset to ‘0’
POR (after tW)
completed
Device deselected (S High) and in Standby
mode
Same as POR
Not significant
1. S remains Low while Reset is Low.
9
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). All usable Status Register bits are 0.
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NUMONYX [ NUMONYX B.V ]
