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M25P80-VMP6TG 参数 Datasheet PDF下载

M25P80-VMP6TG图片预览
型号: M25P80-VMP6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,低电压,串行闪存与75 MHz的SPI总线接口 [8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路时钟
文件页数/大小: 52 页 / 995 K
品牌: NUMONYX [ NUMONYX B.V ]
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Signal description  
M25P80  
2
Signal description  
2.1  
Serial Data output (Q)  
This output signal is used to transfer data serially out of the device. Data is shifted out on the  
falling edge of Serial Clock (C).  
2.2  
2.3  
2.4  
Serial Data input (D)  
This input signal is used to transfer data serially into the device. It receives instructions,  
addresses, and the data to be programmed. Values are latched on the rising edge of Serial  
Clock (C).  
Serial Clock (C)  
This input signal provides the timing of the serial interface. Instructions, addresses, or data  
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on  
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).  
Chip Select (S)  
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high  
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,  
the device will be in the Standby mode (this is not the Deep Power-down mode). Driving  
Chip Select (S) Low enables the device, placing it in the active power mode.  
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any  
instruction.  
2.5  
2.6  
Hold (HOLD)  
The Hold (HOLD) signal is used to pause any serial communications with the device without  
deselecting the device.  
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data  
Input (D) and Serial Clock (C) are Don’t Care.  
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.  
Write Protect (W)  
The main purpose of this input signal is to freeze the size of the area of memory that is  
protected against program or erase instructions (as specified by the values in the BP2, BP1  
and BP0 bits of the Status Register).  
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