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M25P80-VMP6TG 参数 Datasheet PDF下载

M25P80-VMP6TG图片预览
型号: M25P80-VMP6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,低电压,串行闪存与75 MHz的SPI总线接口 [8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路时钟
文件页数/大小: 52 页 / 995 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P80  
Power-up and Power-down  
7
Power-up and Power-down  
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must  
follow the voltage applied on V ) until V reaches the correct value:  
CC  
CC  
V
V
(min) at Power-up, and then for a further delay of t  
at Power-down  
CC  
SS  
VSL  
A safe configuration is provided in Section 3: SPI modes.  
To avoid data corruption and inadvertent write operations during Power-up, a Power On  
Reset (POR) circuit is included. The logic inside the device is held reset while V is less  
CC  
than the POR threshold value, V – all operations are disabled, and the device does not  
WI  
respond to any instruction.  
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase  
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of  
t
has elapsed after the moment that V rises above the V threshold. However, the  
PUW  
CC WI  
correct operation of the device is not guaranteed if, by this time, V is still below V (min).  
CC  
CC  
No Write Status Register, Program or Erase instructions should be sent until the later of:  
t
t
after V passed the V threshold  
CC WI  
PUW  
VSL  
after V passed the V (min) level  
CC  
CC  
These values are specified in Table 8.  
If the delay, t  
, has elapsed, after V has risen above V (min), the device can be  
VSL  
CC  
CC  
selected for READ instructions even if the t  
delay is not yet fully elapsed.  
PUW  
At Power-up, the device is in the following state:  
The device is in the Standby mode (not the Deep Power-down mode).  
The Write Enable Latch (WEL) bit is reset.  
The Write In Progress (WIP) bit is reset.  
Normal precautions must be taken for supply rail decoupling, to stabilize the V feed. Each  
CC  
device in a system should have the V rail decoupled by a suitable capacitor close to the  
CC  
package pins. (Generally, this capacitor is of the order of 100 nF).  
At Power-down, when V drops from the operating voltage, to below the Power On Reset  
CC  
(POR) threshold value, V , all operations are disabled and the device does not respond to  
WI  
any instruction. (The designer needs to be aware that if a Power-down occurs while a Write,  
Program or Erase cycle is in progress, some data corruption can result.)  
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