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M25P80-VMP6TG 参数 Datasheet PDF下载

M25P80-VMP6TG图片预览
型号: M25P80-VMP6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,低电压,串行闪存与75 MHz的SPI总线接口 [8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路时钟
文件页数/大小: 52 页 / 995 K
品牌: NUMONYX [ NUMONYX B.V ]
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Instructions  
M25P80  
6
Instructions  
All instructions, addresses and data are shifted in and out of the device, most significant bit  
first.  
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select  
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most  
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of  
Serial Clock (C).  
The instruction set is listed in Table 4.  
Every instruction sequence starts with a one-byte instruction code. Depending on the  
instruction, this might be followed by address bytes, or by data bytes, or by both or none.  
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),  
Read Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-  
down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence  
is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the  
data-out sequence is being shifted out.  
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status  
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)  
instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the  
instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when  
the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of  
eight.  
All attempts to access the memory array during a Write Status Register cycle, Program  
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program  
cycle or Erase cycle continues unaffected.  
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