M25P64
Description
Figure 1.
Logic diagram
V
CC
D
C
S
Q
M25P64
W/V
PP
HOLD
V
SS
AI07485B
Table 1.
Signal names
Signal name
Function
Direction
Input
C
Serial Clock
D
Serial Data Input
Serial Data Output
Chip Select
Input
Output
Input
Input
Input
Q
S
W/VPP
HOLD
VCC
VSS
Write Protect/Enhanced Program Supply Voltage
Hold
Supply Voltage
Ground
Figure 2.
VDFPN connections
M25P64
S
1
8
7
6
5
V
CC
HOLD
Q
2
3
4
W/V
V
C
D
PP
SS
AI08595B
1. There is an exposed central pad on the underside of the VDFPN package. This is pulled, internally, to VSS
and must not be allowed to be connected to any other voltage or signal line on the PCB.
,
2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
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NUMONYX [ NUMONYX B.V ]
