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M25P64-VME6TPB 参数 Datasheet PDF下载

M25P64-VME6TPB图片预览
型号: M25P64-VME6TPB
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 8MX8, PDSO8, 8 X 6 MM, ROHS COMPLIANT, VDFPN-8]
分类和应用: 闪存存储内存集成电路时钟
文件页数/大小: 50 页 / 943 K
品牌: NUMONYX [ NUMONYX B.V ]
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DC and AC parameters  
M25P64  
Table 14. AC characteristics  
Test conditions specified in Table 10 and Table 11  
Symbol Alt.  
Parameter  
Min.  
Typ.  
Max. Unit  
Clock Frequency for the following instructions: FAST_READ,  
PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR  
fC  
fR  
fC  
D.C.  
50  
20  
MHz  
Clock Frequency for READ instructions  
D.C.  
9
MHz  
ns  
(1)  
tCH  
tCLH Clock High Time  
tCLL Clock Low Time  
(1)  
tCL  
tCLCH  
9
ns  
Clock Rise Time(3) (peak to peak)  
0.1  
0.1  
5
V/ns  
V/ns  
ns  
(2)  
(2)  
tCHCL  
Clock Fall Time(3) (peak to peak)  
tCSS S Active Setup Time (relative to C)  
S Not Active Hold Time (relative to C)  
tDSU Data In Setup Time  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
5
ns  
2
ns  
tDH Data In Hold Time  
5
ns  
S Active Hold Time (relative to C)  
S Not Active Setup Time (relative to C)  
tCSH S Deselect Time  
5
ns  
5
ns  
100  
ns  
(2)  
tSHQZ  
tCLQV  
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
tDIS Output Disable Time  
8
8
ns  
tV Clock Low to Output Valid  
tHO Output Hold Time  
ns  
0
5
5
5
5
ns  
HOLD Setup Time (relative to C)  
HOLD Hold Time (relative to C)  
HOLD Setup Time (relative to C)  
HOLD Hold Time (relative to C)  
tLZ HOLD to Output Low-Z  
tHZ HOLD to Output High-Z  
Write Protect Setup Time  
ns  
ns  
ns  
ns  
(2)  
tHHQX  
tHLQZ  
tWHSL  
tSHWL  
8
8
ns  
(2)  
(4)  
(4)  
ns  
20  
ns  
Write Protect Hold Time  
100  
ns  
(6)  
tVPPHSL  
tW  
Enhanced Program Supply Voltage High to Chip Select Low 200  
Write Status Register Cycle Time  
ns  
5
15  
5
ms  
Page Program Cycle Time (256 Bytes)  
Page Program Cycle Time (n Bytes)  
1.4  
ms  
(5)  
tPP  
0.4+ n*1/256  
Page Program Cycle Time (VPP = VPPH) (256 Bytes)  
Sector Erase Cycle Time  
0.35  
1
ms  
s
3
tSE  
Sector Erase Cycle Time (VPP = VPPH  
)
0.5  
68  
s
Bulk Erase Cycle Time  
160  
160  
s
tBE  
Bulk Erase Cycle Time (VPP = VPPH  
)
35  
s
1. tCH + tCL must be greater than or equal to 1/ fC(max)  
2. Value guaranteed by characterization, not 100% tested in production.  
3. Expressed as a slew-rate.  
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.  
5. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one  
sequence including all the Bytes versus several sequences of only a few Bytes. (1 n 256).  
6. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is  
known.  
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