M25P64
Operating features
4.7
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P64 features the following data protection mechanisms:
●
Power On Reset and an internal timer (t
) can provide protection against inadvertant
PUW
changes while the power supply is outside the operating specification.
●
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
●
●
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
The Write Protect (W/V ) signal allows the Block Protect (BP2, BP1, BP0) bits and
PP
Status Register Write Disable (SRWD) bit to be protected. This is the Hardware
Protected Mode (HPM).
Table 2.
Protected area sizes
Status Register
content
Memory content
BP2 BP1 BP0
Protected area
Unprotected area
Bit
Bit
Bit
0
0
0
0
0
1
0
1
0
none
Upper 64th (2 sectors: 126 and 127) Lower 63/64ths (126 sectors: 0 to 125)
All sectors(1) (128 sectors: 0 to 127)
Upper 32nd (4 sectors: 124 to 127)
Lower 31/32nds (124 sectors: 0 to 123)
Lower 15/16ths (120 sectors: 0 to 119)
Upper sixteenth (8 sectors: 120 to
127)
0
1
1
1
0
0
1
0
1
Lower seven-eighths (112 sectors: 0 to
111)
Upper eighth (16 sectors: 112 to 127)
Upper quarter (32 sectors: 96 to 127)
Lower three-quarters (96 sectors: 0 to
95)
1
1
1
1
0
1
Upper half (64 sectors: 64 to 127)
All sectors (128 sectors: 0 to 127)
Lower half (64 sectors: 0 to 63)
none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
0.
15/50
NUMONYX [ NUMONYX B.V ]
