欢迎访问ic37.com |
会员登录 免费注册
发布采购

M25P40-VMN3TG/4A 参数 Datasheet PDF下载

M25P40-VMN3TG/4A图片预览
型号: M25P40-VMN3TG/4A
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 512KX8, Serial, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 57 页 / 1161 K
品牌: NUMONYX [ NUMONYX B.V ]
 浏览型号M25P40-VMN3TG/4A的Datasheet PDF文件第40页浏览型号M25P40-VMN3TG/4A的Datasheet PDF文件第41页浏览型号M25P40-VMN3TG/4A的Datasheet PDF文件第42页浏览型号M25P40-VMN3TG/4A的Datasheet PDF文件第43页浏览型号M25P40-VMN3TG/4A的Datasheet PDF文件第45页浏览型号M25P40-VMN3TG/4A的Datasheet PDF文件第46页浏览型号M25P40-VMN3TG/4A的Datasheet PDF文件第47页浏览型号M25P40-VMN3TG/4A的Datasheet PDF文件第48页  
DC and AC parameters  
M25P40  
Table 21. AC characteristics (*40 MHz operation, device grade 6, VCC min = 2.3 V)  
Test conditions specified in Table 10 and Table 18  
Symbol  
Alt.  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Clock frequency for the following  
fC  
fR  
fC  
instructions: FAST_READ, PP, SE, BE, DP,  
RES, WREN, RDID, WRDI, RDSR, WRSR  
D.C.  
40  
25  
MHz  
Clock frequency for READ instructions  
Clock High time  
D.C.  
11  
11  
0.1  
0.1  
5
MHz  
ns  
(1)  
tCH  
tCLH  
tCLL  
(1)  
tCL  
Clock Low time  
ns  
(2)  
tCLCH  
Clock Rise time(3) (peak to peak)  
Clock Fall time(3) (peak to peak)  
S Active Setup time (relative to C)  
S Not Active Hold time (relative to C)  
Data In Setup time  
V/ns  
V/ns  
ns  
(2)  
tCHCL  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
tCSS  
5
ns  
tDSU  
tDH  
2
ns  
Data In Hold time  
5
ns  
S Active Hold time (relative to C)  
S Not Active Setup time (relative to C)  
S Deselect time  
5
ns  
5
ns  
tCSH  
tDIS  
tV  
100  
ns  
(2)  
tSHQZ  
Output Disable time  
8
8
ns  
tCLQV  
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
Clock Low to Output Valid  
Output Hold time  
ns  
tHO  
0
5
5
5
5
ns  
HOLD Setup time (relative to C)  
HOLD Hold time (relative to C)  
HOLD Setup time (relative to C)  
HOLD Hold time (relative to C)  
HOLD to Output Low-Z  
ns  
ns  
ns  
ns  
(2)  
tHHQX  
tLZ  
8
8
ns  
(2)  
tHLQZ  
tHZ  
HOLD to Output High-Z  
ns  
(4)  
tWHSL  
Write Protect Setup time  
Write Protect Hold time  
20  
ns  
(4)  
tSHWL  
100  
ns  
(2)  
tDP  
S High to Deep Power-down mode  
3
μs  
S High to Standby Power mode without  
Electronic Signature Read  
(2)  
tRES1  
30  
μs  
μs  
S High to Standby Power mode with  
Electronic Signature Read  
(2)  
tRES2  
30  
1. tCH + tCL must be greater than or equal to 1/ fC  
2. Value guaranteed by characterization, not 100% tested in production.  
3. Expressed as a slew-rate.  
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.  
Note:  
*40 MHz = max frequency device operation in extended Vcc range 2.3 to 2.7 V.  
44/57