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M25P20-VMP3TP/X 参数 Datasheet PDF下载

M25P20-VMP3TP/X图片预览
型号: M25P20-VMP3TP/X
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位,低电压,串行闪存与50MHz的SPI总线接口 [2 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 50 页 / 964 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P20  
DC and AC parameters  
Table 19. AC Characteristics (40MHz Operation, Device Grade 6)  
40MHz available for products marked since week 20 of 2004, only(1)  
Test conditions specified in Table 10 and Table 17  
Symbol  
Alt.  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Clock Frequency for the following  
fC  
fR  
fC  
instructions: FAST_READ, PP, SE, BE,  
DP, RES, WREN, WRDI, RDSR, WRSR  
D.C.  
40  
20  
MHz  
Clock Frequency for READ instructions  
Clock High Time  
D.C.  
11  
11  
0.1  
0.1  
5
MHz  
ns  
(2)  
tCH  
tCLH  
tCLL  
(2)  
tCL  
Clock Low Time  
ns  
(3)  
tCLCH  
Clock Rise Time(4) (peak to peak)  
Clock Fall Time(4) (peak to peak)  
S Active Setup Time (relative to C)  
S Not Active Hold Time (relative to C)  
Data In Setup Time  
V/ns  
V/ns  
ns  
(3)  
tCHCL  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
tCSS  
5
ns  
tDSU  
tDH  
2
ns  
Data In Hold Time  
5
ns  
S Active Hold Time (relative to C)  
S Not Active Setup Time (relative to C)  
S Deselect Time  
5
ns  
5
ns  
tCSH  
tDIS  
tV  
100  
ns  
(3)  
tSHQZ  
Output Disable Time  
9
9
ns  
tCLQV  
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
Clock Low to Output Valid  
Output Hold Time  
ns  
tHO  
0
5
5
5
5
ns  
HOLD Setup Time (relative to C)  
HOLD Hold Time (relative to C)  
HOLD Setup Time (relative to C)  
HOLD Hold Time (relative to C)  
HOLD to Output Low-Z  
ns  
ns  
ns  
ns  
(3)  
tHHQX  
tLZ  
9
9
ns  
(3)  
tHLQZ  
tHZ  
HOLD to Output High-Z  
ns  
(5)  
tWHSL  
Write Protect Setup Time  
Write Protect Hold Time  
20  
ns  
(5)  
tSHWL  
100  
ns  
(3)  
tDP  
S High to Deep Power-down Mode  
3
μs  
S High to Standby Mode without  
Electronic Signature Read  
(3)  
tRES1  
3 or 30(6)  
μs  
μs  
S High to Standby Mode with Electronic  
Signature Read  
(3)  
tRES2  
1.8 or 30(6)  
1. Details of how to find the date of marking are given in Application Note, AN1995.  
2. tCH + tCL must be greater than or equal to 1/ fC  
3. Value guaranteed by characterization, not 100% tested in production.  
4. Expressed as a slew-rate.  
5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.  
6. It is 30µs in devices produced with the “X” process technology. Details of how to find the process letter on  
the device marking are given in the Application note AN1995.  
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