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M25P20-VMP3G/X 参数 Datasheet PDF下载

M25P20-VMP3G/X图片预览
型号: M25P20-VMP3G/X
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位,低电压,串行闪存与50MHz的SPI总线接口 [2 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 50 页 / 964 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P20  
Instructions  
Table 7.  
Protection Modes  
Memory Content  
W
Signal  
SRWD  
Bit  
Write Protection of the  
Mode  
Unprotected  
Status Register  
Protected Area(1)  
Area(1)  
1
0
0
0
Status Register is Writable  
(if the WREN instruction  
has set the WEL bit)  
Protected against  
Page Program,  
Sector Erase and  
Bulk Erase  
Ready to accept  
Page Program and  
Sector Erase  
Software  
Protected  
(SPM)  
The values in the SRWD,  
BP1 and BP0 bits can be  
changed  
instructions  
1
1
Status Register is  
Hardware write protected  
Protected against  
Page Program,  
Sector Erase and  
Bulk Erase  
Ready to accept  
Page Program and  
Sector Erase  
Hardware  
Protected  
(HPM)  
0
1
The values in the SRWD,  
BP1 and BP0 bits cannot  
be changed  
instructions  
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.  
The protection features of the device are summarized in Table 7.  
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial  
delivery state), it is possible to write to the Status Register provided that the Write Enable  
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless  
of the whether Write Protect (W) is driven High or Low.  
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two  
cases need to be considered, depending on the state of Write Protect (W):  
If Write Protect (W) is driven High, it is possible to write to the Status Register provided  
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable  
(WREN) instruction.  
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even  
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)  
instruction. (Attempts to write to the Status Register are rejected, and are not accepted  
for execution). As a consequence, all the data bytes in the memory area that are  
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,  
are also hardware protected against data modification.  
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be  
entered:  
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)  
Low  
or by driving Write Protect (W) Low after setting the Status Register Write Disable  
(SRWD) bit.  
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write  
Protect (W) High.  
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can  
never be activated, and only the Software Protected Mode (SPM), using the Block Protect  
(BP1, BP0) bits of the Status Register, can be used.  
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