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M25P128-VME6TP 参数 Datasheet PDF下载

M25P128-VME6TP图片预览
型号: M25P128-VME6TP
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位(多电平),低电压,串行闪存与50MHz的SPI总线接口 [128 Mbit (Multilevel), low-voltage, Serial Flash memory with 50-MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 45 页 / 864 K
品牌: NUMONYX [ NUMONYX B.V ]
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DC and AC parameters  
M25P128  
Table 14. AC characteristics (continued)  
Test conditions specified in Table 10 and Table 11  
Symbol  
Alt.  
Parameter  
Min. Typ.  
Max.  
250  
Unit  
Bulk Erase Cycle Time  
105  
tBE  
s
Bulk Erase Cycle Time (VPP = VPPH  
)
56(2)  
1. tCH and tCL must be greater than or equal to 1/fC (max).  
2. Value is guaranteed by characterization, not 100% tested in production.  
3. Expressed as a slew-rate.  
4. Only applicable as a constraint for WRSR instruction when SRWD is set to 1.  
5. VPPH should be kept at a valid level until the program or erase operation has completed and its result  
(success or failure) is known.  
6. Due to the Multi Level Cell technology, when using the Page Program (PP) instruction to program  
consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus  
several sequences of only a few Bytes. If only a single byte is programmed, the estimated programming  
time is close to the time needed to program a full page of 256 Bytes. Therefore, it is highly recommended  
to use the Page Program (PP) instruction with a sequence of 256 consecutive Bytes. (1 n 256)  
Figure 20. Serial input timing  
tSHSL  
S
tCHSL  
tSLCH  
tCHSH  
tSHCH  
C
tDVCH  
tCHCL  
tCHDX  
tCLCH  
MSB IN  
LSB IN  
D
Q
High Impedance  
AI01447C  
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