M25P128
Instructions
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/V ) is driven High or Low.
PP
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W/V ):
PP
●
If Write Protect (W/V ) is driven High, it is possible to write to the Status Register
PP
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
●
If Write Protect (W/V ) is driven Low, it is not possible to write to the Status Register
PP
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/V ) Low
PP
●
or by driving Write Protect (W/V ) Low after setting the Status Register Write Disable
PP
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W/V ) High.
PP
If Write Protect (W/V ) is permanently tied High, the Hardware Protected Mode (HPM) can
PP
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Figure 12. Write Status Register (WRSR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
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NUMONYX [ NUMONYX B.V ]
