欢迎访问ic37.com |
会员登录 免费注册
发布采购

M25P10-AVMN6TP/Y 参数 Datasheet PDF下载

M25P10-AVMN6TP/Y图片预览
型号: M25P10-AVMN6TP/Y
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位,串行闪存, 50MHz的SPI总线接口 [1 Mbit, serial Flash memory, 50 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 51 页 / 989 K
品牌: NUMONYX [ NUMONYX B.V ]
 浏览型号M25P10-AVMN6TP/Y的Datasheet PDF文件第22页浏览型号M25P10-AVMN6TP/Y的Datasheet PDF文件第23页浏览型号M25P10-AVMN6TP/Y的Datasheet PDF文件第24页浏览型号M25P10-AVMN6TP/Y的Datasheet PDF文件第25页浏览型号M25P10-AVMN6TP/Y的Datasheet PDF文件第27页浏览型号M25P10-AVMN6TP/Y的Datasheet PDF文件第28页浏览型号M25P10-AVMN6TP/Y的Datasheet PDF文件第29页浏览型号M25P10-AVMN6TP/Y的Datasheet PDF文件第30页  
Instructions
M25P10-A
6.8
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is t
PP
) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP1, BP0) bits (see
and
is not executed.
26/51