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M25P10-AVMB6TP/Y 参数 Datasheet PDF下载

M25P10-AVMB6TP/Y图片预览
型号: M25P10-AVMB6TP/Y
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位,串行闪存, 50MHz的SPI总线接口 [1 Mbit, serial Flash memory, 50 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路时钟
文件页数/大小: 51 页 / 989 K
品牌: NUMONYX [ NUMONYX B.V ]
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Instructions  
M25P10-A  
6.2  
Write Disable (WRDI)  
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.  
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the  
instruction code, and then driving Chip Select (S) High.  
The Write Enable Latch (WEL) bit is reset under the following conditions:  
Power-up  
Write Disable (WRDI) instruction completion  
Write Status Register (WRSR) instruction completion  
Page Program (PP) instruction completion  
Sector Erase (SE) instruction completion  
Bulk Erase (BE) instruction completion  
Figure 8.  
Write Disable (WRDI) instruction sequence  
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction  
High Impedance  
AI03750D  
18/51  
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