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M25P10-AVMB3T/X 参数 Datasheet PDF下载

M25P10-AVMB3T/X图片预览
型号: M25P10-AVMB3T/X
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位,串行闪存, 50MHz的SPI总线接口 [1 Mbit, serial Flash memory, 50 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 51 页 / 989 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P10-A  
DC and AC parameters  
Table 19. AC characteristics (40 MHz operation, device grade 6)  
40 MHz available for products marked since week 20 of 2004, only(1)  
Test conditions specified in Table 10 and Table 12  
Symbol Alt.  
Parameter  
Min  
Typ  
Max  
Unit  
Clock frequency for the following instructions:  
FAST_READ, PP, SE, BE, DP, RES, WREN,  
WRDI, RDSR, WRSR  
fC  
fR  
fC  
D.C.  
40  
20  
MHz  
Clock frequency for READ instructions  
D.C.  
11  
11  
0.1  
0.1  
5
MHz  
ns  
(2)  
tCH  
tCLH Clock High time  
tCLL Clock Low time  
(2)  
tCL  
ns  
(3)  
tCLCH  
tCHCL  
Clock Rise time(4) (peak to peak)  
V/ns  
V/ns  
ns  
(3)  
Clock Fall time(4) (peak to peak)  
tCSS S Active Setup time (relative to C)  
S Not Active Hold time (relative to C)  
tDSU Data In Setup time  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
5
ns  
2
ns  
tDH Data In Hold time  
5
ns  
S Active Hold time (relative to C)  
S Not Active Setup time (relative to C)  
tCSH S Deselect time  
5
ns  
5
ns  
100  
ns  
(3)  
tSHQZ  
tCLQV  
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
tDIS Output Disable time  
9
9
ns  
tV  
tHO Output Hold time  
HOLD Setup time (relative to C)  
Clock Low to Output Valid  
ns  
0
5
5
5
5
ns  
ns  
HOLD Hold time (relative to C)  
HOLD Setup time (relative to C)  
HOLD Hold time (relative to C)  
tLZ HOLD to Output Low-Z  
tHZ HOLD to Output High-Z  
Write Protect Setup time  
ns  
ns  
ns  
(3)  
tHHQX  
9
9
ns  
(3)  
tHLQZ  
tWHSL  
tSHWL  
ns  
(5)  
(5)  
20  
ns  
Write Protect Hold time  
100  
ns  
(3)  
tDP  
S High to Deep Power-down mode  
3
µs  
S High to Standby mode without Read  
Electronic Signature  
(3)  
(3)  
tRES1  
3 or 30(6)  
µs  
S High to Standby mode with Read Electronic  
Signature  
tRES2  
1.8 or 30(6) µs  
1. Details of how to find the date of marking are given in application note, AN1995.  
2. tCH + tCL must be greater than or equal to 1/ fC.  
3. Value guaranteed by characterization, not 100% tested in production.  
4. Expressed as a slew-rate.  
5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.  
6. It is 30 µs in devices produced with the ‘X’ and ‘Y’ process technology codes. Details of how to find the  
process letter on the device marking are given in the application note AN1995.  
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