M25P10-A
Instructions
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Figure 11. Write Status Register (WRSR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
Table 7.
Protection modes
Memory content
W
signal
SRWD
bit
Write protection of the
Status Register
Mode
Unprotected
area(1)
Protected area(1)
1
0
0
0
Status Register is writable (if
the WREN instruction has set
the WEL bit)
Protected against Ready to accept
Page Program, Page Program
Sector Erase and and Sector Erase
Software
protected
(SPM)
The values in the SRWD, BP1
and BP0 bits can be changed
Bulk Erase
instructions
1
1
Status Register is hardware
write protected
Protected against Ready to accept
Page Program, Page Program
Sector Erase and and Sector Erase
Bulk Erase instructions
Hardware
protected
(HPM)
0
1
The values in the SRWD, BP1
and BP0 bits cannot be
changed
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
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NUMONYX [ NUMONYX B.V ]
