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M25P10-AVMP3P/X 参数 Datasheet PDF下载

M25P10-AVMP3P/X图片预览
型号: M25P10-AVMP3P/X
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位,串行闪存, 50MHz的SPI总线接口 [1 Mbit, serial Flash memory, 50 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 51 页 / 989 K
品牌: NUMONYX [ NUMONYX B.V ]
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Instructions  
M25P10-A  
6.11  
Deep Power-down (DP)  
Executing the Deep Power-down (DP) instruction is the only way to put the device in the  
lowest consumption mode (the Deep Power-down mode). It can also be used as a software  
protection mechanism, while the device is not in active use, as in this mode, the device  
ignores all write, program and erase instructions.  
Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode  
(if there is no internal cycle currently in progress). But this mode is not the Deep Power-  
down mode. The Deep Power-down mode can only be entered by executing the Deep  
Power-down (DP) instruction, to reduce the standby current (from I  
to I  
, as specified  
CC1  
CC2  
in Table 14).  
To take the device out of Deep Power-down mode, the Release from Deep Power-down and  
Read Electronic Signature (RES) instruction must be issued. No other instruction must be  
issued while the device is in Deep Power-down mode.  
The Release from Deep Power-down, and Read Electronic Signature (RES) instruction and  
the Read Identification (RDID) instruction also allow the electronic signature of the device to  
be output on Serial Data output (Q).  
The Deep Power-down mode automatically stops at power-down, and the device always  
powers-up in the Standby mode.  
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed  
by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the  
entire duration of the sequence.  
The instruction sequence is shown in Figure 17.  
Chip Select (S) must be driven High after the eighth bit of the instruction code has been  
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as  
Chip Select (S) is driven High, it requires a delay of t before the supply current is reduced  
DP  
to I  
and the Deep Power-down mode is entered.  
CC2  
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in  
progress, is rejected without having any effects on the cycle that is in progress.  
Figure 17. Deep Power-down (DP) instruction sequence  
S
tDP  
0
1
2
3
4
5
6
7
C
D
Instruction  
Standby mode  
Deep Power-down mode  
AI03753D  
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