M25P05
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
At the end of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) or Write Status Register
(WRSR) instruction, Chip Select (S) must be driv-
en High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is,
Chip Select (S) must driven High when the number
of clock pulses after Chip Select (S) being driven
Low is an exact multiple of eight.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
The instruction set is listed in Table 4.
Depending on the instruction, the one-byte in-
struction code is followed by address bytes, or by
data bytes, or by both or none. Chip Select (S)
must be driven High after the last bit of the instruc-
tion sequence has been shifted in.
Table 4. Instruction Set
Instruction
WREN
WRDI
RDSR
WRSR
READ
PP
Description
One-byte Instruction Code
0000 0110
Write Enable
Write Disable
0000 0100
Read Status Register
Write Status Register
Read Data Bytes
Page Program
0000 0101
0000 0001
0000 0011
0000 0010
SE
Sector Erase
1101 1000
BE
Bulk Erase
1100 0111
DP
Deep Power-down
1011 1001
RES
Release from Deep Power-down, and Read Electronic Signature
1010 1011
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NUMONYX [ NUMONYX B.V ]
