Initial delivery state
M25P05-A
Figure 20. Power-up timing
V
CC
V
(max)
CC
Program, erase and write commands are rejected by the device
Chip selection not allowed
V
(min)
CC
tVSL
Read access allowed
Device fully
accessible
Reset state
of the
device
V
WI
tPUW
time
AI04009C
Table 8.
Symbol
Power-up timing and V threshold
WI
Parameter
Min
Max
Unit
(1)
tVSL
VCC(min) to S low
10
1
µs
ms
V
(1)
tPUW
Time delay to Write instruction
Write inhibit voltage
10
2
(1)
VWI
1
1. These parameters are characterized only.
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). The status register contains 00h (all status register bits are 0).
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