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M24512-DFMC6TG 参数 Datasheet PDF下载

M24512-DFMC6TG图片预览
型号: M24512-DFMC6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位,低电压,串行闪存与54 MHz的SPI总线接口 [128-Mbit, low-voltage, serial flash memory with 54-MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 47 页 / 905 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P128  
Instructions  
6
Instructions  
All instructions, addresses and data are shifted in and out of the device, most significant bit  
first.  
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select  
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most  
significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of  
Serial Clock (C).  
The instruction set is listed in Table 4.  
Every instruction sequence starts with a one-byte instruction code. Depending on the  
instruction, this might be followed by address bytes, or by data bytes, or by both or none.  
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),  
Read Status Register (RDSR) or Read Identification (RDID) instruction, the shifted-in  
instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High  
after any bit of the data-out sequence is being shifted out.  
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status  
Register (WRSR), Write Enable (WREN) or Write Disable (WRDI), Chip Select (S) must be  
driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not  
executed. That is, Chip Select (S) must driven High when the number of clock pulses after  
Chip Select (S) being driven Low is an exact multiple of eight.  
All attempts to access the memory array during a Write Status Register cycle, Program  
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program  
cycle or Erase cycle continues unaffected.  
Table 4.  
Instruction set  
Description  
One-byte Instruction Address Dummy  
Data  
Instruction  
Code  
Bytes  
Bytes  
Bytes  
WREN  
WRDI  
RDID  
Write Enable  
0000 0110  
06h  
04h  
9Fh  
05h  
01h  
03h  
0
0
0
0
0
3
0
0
0
0
0
0
0
0
Write Disable  
0000 0100  
1001 1111  
0000 0101  
0000 0001  
0000 0011  
Read Identification  
Read Status Register  
Write Status Register  
Read Data Bytes  
1 to 3  
1 to  
1
RDSR  
WRSR  
READ  
1 to ∞  
Read Data Bytes at Higher  
Speed  
FAST_READ  
0000 1011  
0Bh  
3
1
1 to ∞  
PP  
SE  
BE  
Page Program  
Sector Erase  
Bulk Erase  
0000 0010  
1101 1000  
1100 0111  
02h  
D8h  
C7h  
3
3
0
0
0
0
1 to 256  
0
0
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