Numonyx™ Wireless Flash Memory (W18)
Figure 19: Reset Operations Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
RST# [P]
RST# [P]
RST# [P]
VCC
read mode
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
7.4
AC I/O Test Conditions
Figure 20: AC Input/Output Reference Waveform
VCCQ
Test Points
Input
VCCQ/2
VCCQ/2
Output
0V
Note: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed
conditions are when VCC = VCCMin.
Figure 21: Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
Note: See Table 18 on page 43 for component values.
Datasheet
44
November 2007
Order Number: 290701-18
NUMONYX [ NUMONYX B.V ]
