P30
10.3.1
10.3.2
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
Latency Count
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is to be driven onto DQ[15:0]. The input clock frequency is used to
determine this value and Figure 26 shows the data output latency for the different
settings of LC. The maximum Latency Count for P30 would be Code 4 based on the Max
Clock frequency specification of 52 mhz, and there will be zero WAIT States when
bursting within the word line. Please also refer to “End of Word Line (EOWL)
Considerations” on page 55 for more information on EOWL.
Refer to Table 26, “Latency Count (LC) and Frequency Support” on page 51 for Latency
Code Settings.
Datasheet
50
November 2007
Order Number: 306666-11
NUMONYX [ NUMONYX B.V ]
