P30
7.2
Capacitance
Table 15: Capacitance
Parameter
Signals
Min
Typ
Max
Unit
Condition
Notes
Address, Data,
CE#, WE#, OE#,
RST#, CLK, ADV#,
WP#
Typ temp = 25 °C,
Max temp = 85 °C,
VCC = (0 V - 2.0 V),
VCCQ = (0 V - 3.6 V),
Discrete silicon die
Input Capacitance
Output Capacitance
2
2
6
4
7
5
pF
pF
1,2,3
Data, WAIT
Notes:
1.
Capacitance values are for a single die; for 2-die and 4-die stacks, multiply the capacitance values by the number of
dies in the stack.
2.
3.
Sampled, but not 100% tested.
Silicon die capacitance only; add 1 pF for discrete packages.
7.3
AC Read Specifications
Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
Read cycle time
85
-
-
85
85
25
150
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to output valid
CE# low to output valid
OE# low to output valid
-
-
1,2
1
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
-
0
0
-
1,3
1,2,3
-
24
24
-
1,3
Output hold from first occurring address, CE#, or
OE# change
R10
tOH
0
-
ns
R11
R12
R13
R15
tEHEL
tELTV
tEHTZ
tGLTV
CE# pulse width high
20
-
-
ns
ns
ns
ns
ns
ns
1
CE# low to WAIT valid
CE# high to WAIT high-Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
17
20
17
-
-
1,3
1
-
R16
R17
tGLTX
tGHTZ
0
-
1,3
20
Latching Specifications
R101
R102
R103
R104
R105
R106
tAVVH
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
Address setup to ADV# high
CE# low to ADV# high
10
10
-
-
-
ns
ns
ns
ns
ns
ns
ADV# low to output valid
ADV# pulse width low
85
-
1
10
10
9
ADV# pulse width high
Address hold from ADV# high
-
-
1,4
November 2007
Order Number: 306666-11
Datasheet
29
NUMONYX [ NUMONYX B.V ]
