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JS48F4400P0Z0C0 参数 Datasheet PDF下载

JS48F4400P0Z0C0图片预览
型号: JS48F4400P0Z0C0
PDF下载: 下载PDF文件 查看货源
内容描述: StrataFlash㈢蜂窝内存 [StrataFlash㈢ Cellular Memory]
分类和应用: 蜂窝
文件页数/大小: 139 页 / 2133 K
品牌: NUMONYX [ NUMONYX B.V ]
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Numonyx™ StrataFlash® Cellular Memory (M18)  
The Status Register should be polled for SR0 = 0 (Buffer Ready for Data) to determine  
when the array programming has completed, and the write buffer is again available for  
loading. The internal address is automatically incremented to enable subsequent array  
programming to continue from where the previous buffer-fill/array-program sequence  
ended within the block. This cycle can be repeated to program the entire block.  
To exit the Program/Verify Phase, write FFFFh to an address outside of the block.  
9.6.3.3  
Exit Phase  
The Status Register should be polled for SR7 = 1 (Device Ready) indicating the BEFP  
algorithm has finished running, and the device has returned to normal operation. A full  
error check should be performed to ensure the block was programmed successfully.  
9.7  
Block Erase Operations  
Erasing a block changes ‘zeros’ to ‘ones. To change ones to zeros, a program operation  
must be performed (see Section 9.6, “Programming Operations). Erasing is performed  
on a block basis— an entire block is erased each time an erase command sequence is  
issued. Once a block is fully erased, all addressable locations within that block read as  
logical ‘ones’ (FFFFh).  
Only one block-erase operation can occur at a time. A block-erase operation is not  
permitted during Program Suspend.  
To perform a block-erase operation, issue the Block Erase command sequence at the  
desired block address. Table 41 shows the two-cycle Block Erase command sequence.  
Table 41: Block-Erase Command Bus Cycles  
Setup Write Cycle  
Confirm Write Cycle  
Address Bus Data Bus  
Block Address 00D0h  
Command  
Address Bus  
Data Bus  
Block Erase  
Device Address  
0020h  
Caution:  
All block-erase operations require the addressed block to be unlocked, and a  
valid voltage applied to VPP throughout the block-erase operation. Otherwise,  
the operation aborts, setting the appropriate Status Register error bit(s).  
The Erase Confirm command latches the address of the block to be erased. The  
addressed block is preconditioned (programmed to all zeros), erased, and then verified.  
The read mode of the addressed partition is automatically changed to Read Status  
Register mode, and remains in effect until another read-mode command is issued.  
Note:  
Issuing the Read Status Register command to another partition switches that partition’s  
read mode to the Read Status Register, thereby allowing block-erase progress to be  
monitored from that partition’s address. SR0 indicates whether the addressed partition  
or other partition is erasing.  
During a block-erase operation, the Status Register indicates a busy status (SR7 = 0).  
Upon completion, the Status Register indicates a ready status (SR7 = 1). The Status  
Register should be checked for any errors, and then cleared.  
The only valid commands during a block erase operation are Read Array, Read Device  
Information, CFI Query, Read Status and Erase Suspend. After the block-erase  
operation has completed, any valid command can be issued.  
Datasheet  
92  
April 2008  
309823-10