Numonyx™ StrataFlash® Cellular Memory (M18)
Table 53: System Interface Information (Sheet 2 of 2)
Offset
Length
Description
Address
Hex Code
Value
8192 µs (256, 512 Mbit -
90 nm; 128, 256, 512
Mbit - 65 nm)
4096 µs (1024 Mbit - 65
nm)
--02 (256, 512 Mbit - 90 nm;
128, 256, 512 Mbit - 65 nm)
--01 (1024 Mbit - 65 nm)
“n” such that maximum buffer
write timeout = 2n times typical.
24h
1
24
“n” such that maximum block
25h
26h
1
1
25
26
--02
--00
4 s
NA
erase timeout = 2n times typical.
“n” such that maximum chip
erase timeout = 2n times typical.
12.4
Device Geometry Definition
Table 54: Device Geometry Definition
Offset
Length
Description
n such that device size in bytes = 2n.
Address
27:
Hex Code
Value
27h
1
Flash device interface code assignment: n such that n + 1 specifies
the bit field that represents the flash device width capabilities as
described here:
Table 55, “Device
Geometry Definition: Addr,
Hex Code, Value” on
page 114
7
6
5
4
3
x64
11
—
2
x32
10
—
1
x16
9
0
x8
8
28h
2
—
15
—
—
14
—
—
13
—
—
12
—
28:
--01
x16
—
—
29:
--00
2A:
2B:
--0A
--00
2Ah
2Ch
2
1
n such that maximum number of bytes in write buffer = 2n.
1024
Number of erase block regions (x) within the device:
1) x = 0 means no erase blocking; the device erases in bulk.
2) x specifies the number of device regions with one or more
contiguous, same-size erase blocks.
2C:
3) Symmetrically blocked partitions have one blocking region.
2D:
2E:
2F:
30:
Erase block region 1 information:
bits 0 - 15 = y, y + 1 = number of identical-size erase blocks.
bits 16 - 31 = z, region erase block(s) size are z x 256 bytes.
2Dh
31h
35h
4
4
4
Table 55, “Device
Geometry
Definition: Addr,
Hex Code, Value”
on page 114
31:
32:
33:
34:
Reserved for future erase block region information.
Reserved for future erase block region information.
35:
36:
37:
38:
April 2008
309823-10
Datasheet
113
NUMONYX [ NUMONYX B.V ]
