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JS28F640P33T85 参数 Datasheet PDF下载

JS28F640P33T85图片预览
型号: JS28F640P33T85
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 4MX16, 85ns, PDSO56, 14 X 20 MM, LEAD FREE, TSOP-56]
分类和应用: 光电二极管内存集成电路闪存
文件页数/大小: 96 页 / 1379 K
品牌: NUMONYX [ NUMONYX B.V ]
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Numonyx™ StrataFlash® Embedded Memory (P33)  
stored to sequential buffer locations starting at address 0x00. Programming of the  
buffer contents to the flash memory array starts as soon as the buffer is full. If the  
number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF.  
Caution:  
The buffer must be completely filled for programming to occur. Supplying an  
address outside of the current block's range during a buffer-fill sequence  
causes the algorithm to exit immediately. Any data previously loaded into the  
buffer during the fill cycle is not programmed into the array.  
The starting address for data entry must be buffer size aligned, if not the BEFP  
algorithm will be aborted and the program fails and (SR[4]) flag will be set.  
Data words from the write buffer are directed to sequential memory locations in the  
flash memory array; programming continues from where the previous buffer sequence  
ended. The host programming system must poll SR[0] to determine when the buffer  
program sequence completes. SR[0] cleared indicates that all buffer data has been  
transferred to the flash array; SR[0] set indicates that the buffer is not available yet for  
the next fill cycle. The host system may check full status for errors at any time, but it is  
only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write  
cycles should be issued to the device until SR[0] = 0 and the device is ready for the  
next buffer fill.  
Note:  
Any spurious writes are ignored after a buffer fill operation and when internal program  
is proceeding.  
The host programming system continues the BEFP algorithm by providing the next  
group of data words to be written to the buffer. Alternatively, it can terminate this  
phase by changing the block address to one outside of the current block’s range.  
The Program/Verify phase concludes when the programmer writes to a different block  
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the  
device enters the BEFP Exit phase.  
11.3.3.4  
11.3.4  
BEFP Exit Phase  
When SR[7] is set, the device has returned to normal operating conditions. A full status  
check should be performed at this time to ensure the entire block programmed  
successfully. When exiting the BEFP algorithm with a block address change, the read  
mode will not change. After BEFP exit, any valid command can be issued to the device.  
Program Suspend  
Issuing the Program Suspend command while programming suspends the  
programming operation. This allows data to be accessed from the device other than the  
one being programmed. The Program Suspend command can be issued to any device  
address. A program operation can be suspended to perform reads only. Additionally, a  
program operation that is running during an erase suspend can be suspended to  
perform a read operation (see Figure 34, “Program Suspend/Resume Flowchart” on  
page 70).  
When a programming operation is executing, issuing the Program Suspend command  
requests the WSM to suspend the programming algorithm at predetermined points. The  
device continues to output Status Register data after the Program Suspend command is  
issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend  
latency is specified in Section 7.5, “Program and Erase Characteristics” on page 39.  
To read data from the device, the Read Array command must be issued. Read Array,  
Read Status Register, Read Device Identifier, CFI Query, and Program Resume are valid  
commands during a program suspend.  
November 2007  
Order Number: 314749-05  
Datasheet  
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