Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
4.3
Signal Descriptions
Table 3 lists the active signals used on J3 65 nm SBC and provides a description of
each.
Table 3:
Signal Descriptions for J3 65 nm SBC
Symbol
Type
Name and Function
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This
address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is
turned off when BYTE# is high).
A0
Input
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle:
32-Mbit — A[21:1]
64-Mbit— A[22:1]
128-Mbit — A[23:1]
A[MAX:1]
Input
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands
during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data
is internally latched during write operations.
Input/
Output
DQ[7:0]
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15:8] float in x8 mode.
Input/
Output
DQ[15:8]
CHIP ENABLE: Activates the 32-, 64-, 128-Mbit devices’ control logic, input buffers, decoders, and
sense amplifiers. When the device is de-selected (see Table 17, “Chip Enable Truth Table
for 32-, 64-, 128-Mb” on page 30), power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection occurs with the first
edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of
CE0, CE1, or CE2 that disables the device (see Table 17, “Chip Enable Truth Table for
32-, 64-, 128-Mb” on page 30).
CE[2:0]
RP#
Input
RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
Input
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE#
WE#
Input
Input
OE# is active low.
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
Addresses and data are latched on the rising edge of WE#.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the Status signal, see the
Configurations command and Section 9.6, “Status Signal” on page 40. STS is to be tied
to VCCQ with a pull-up resistor.
Open Drain
Output
STS
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while
D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places
the device in x16 mode, and turns off the A0 input buffer, the address A1 becomes the lowest-order
address bit.
BYTE#
Input
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
VPEN
VCC
Input
With V
≤ V
, memory contents cannot be altered.
PEN
PENLK
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when V
CC
≤ V
.
Power
Lko
Caution: Device operation at invalid Vcc voltages should not be attempted.
I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to V
GROUND: Ground reference for device logic voltages. Connect to system ground.
No Connect: Lead is not internally connected; it may be driven or floated.
VCCQ
VSS
NC
Power
Supply
—
.
CC
Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device
functionality and enhancement.
RFU
—
Datasheet
18
May 2009
208032-01
NUMONYX [ NUMONYX B.V ]
