P30-65nm
3.0
Ballouts
Figure 4: 56-Lead TSOP Pinout (512-Mbit and 1-Gbit Densities)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WAIT
A17
1
A16
A15
2
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
ADV#
CLK
3
A14
A13
A12
A11
A10
A9
4
5
6
7
8
9
A23
A22
A21
VSS
RFU
WE#
WP#
A20
A19
A18
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NumonyxTM
™
AxcellTM P30 Flash Memory
RST#
VPP
56-Lead TSOP Pinout
14 mm x 20 mm
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE#
VSS
Top View
A7
A6
A5
A4
A3
A2
A24
A25
A26
CE#
A1
Notes:
1.
2.
3.
4.
A1 is the least significant address bit.
A25 is valid for 512-Mbit densities and above; otherwise, it is a no connect (NC).
A26 is valid for 1-Gbit density; otherwise, it is a no connect (NC).
No Internal Connection on V Pin 13; it may be driven or floated. For legacy designs, pin can be tied to Vcc.
CC
Datasheet
10
Aug 2009
Order Number: 208042-02