P30
The P30 protection register allows unique flash device identification that can be used to
increase system security. The individual Block Lock feature provides zero-latency block
locking and unlocking. In addition, the P30 device also has four pre-defined spaces in
the main array that can be configured as One-Time Programmable (OTP).
1.3
Virtual Chip Enable Description
The P30 512Mbit devices employ a Virtual Chip Enable which combines two 256-Mbit
die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA and
TSOP packages. (Refer to Figure 9 on page 21 and Figure 10 on page 21). Address A24
(Quad+ package) or A25 (Easy BGA and TSOP packages) is then used to select
between the die pair with F1-CE# / CE# asserted depending upon the package option
used. When chip enable is asserted and QUAD+ A24 (Easy BGA/TSOP A25) is low (VIL),
The lower parameter die is selected; when chip enable is asserted and QUAD+ A24
(Easy BGA/TSOP A25) is high (VIH), the upper parameter die is selected. Refer to
Table 1 and Table 2 for additional details.
Table 1:
Virtual Chip Enable Truth Table for 512 Mb (QUAD+ Package)
Die Selected
F1-CE#
A24
Lower Param Die
Upper Param Die
L
L
L
H
Table 2:
Virtual Chip Enable Truth Table for 512 Mb (Easy BGA & TSOP Packages)
Die Selected
CE#
A25
Lower Param Die
Upper Param Die
L
L
L
H
Datasheet
6
August 2008
306666-12
NUMONYX [ NUMONYX B.V ]
