P30-65nm
1.3
Virtual Chip Enable Description
The P30-65nm 512Mbit devices employ a Virtual Chip Enable which combines two 256-
Mbit die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA
packages. (Refer to Figure 9 on page 18 and Figure 10 on page 18). The maximum
address bit is then used to select between the die pair with F1-CE# / CE# asserted
depending upon the package option used. When chip enable is asserted and The
maximum address bit is low (VIL), The lower parameter die is selected; when chip
enable is asserted and the maximum address bit is high (VIH), the upper parameter die
is selected. Refer to Table 1 and Table 2 for additional details.
Table 1:
Virtual Chip Enable Truth Table for 512 Mb (QUAD+ Package)
Die Selected
F1-CE#
A24
Lower Param Die
Upper Param Die
L
L
L
H
Table 2:
Virtual Chip Enable Truth Table for 512 Mb (Easy BGA Packages)
Die Selected
CE#
A25
Lower Param Die
Upper Param Die
L
L
L
H
Datasheet
6
Apr 2009
Order Number: 320002-08
NUMONYX [ NUMONYX B.V ]
