P30
4.0
Ballout and Signal Descriptions
4.1
Signal Ballout
Figure 6: 56-Lead TSOP Pinout (64/128/256/512- Mbit)
WAIT
A17
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
A16
A15
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
ADV#
CLK
A14
A13
A12
A11
A10
A9
A23
A22
A21
VSS
VCC
WE#
WP#
A20
A19
A18
A8
A7
A6
A5
A4
A3
A2
A24
A25
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Intel StrataFlash®
Embedded Memory (P30)
RST#
VPP
56-Lead TSOP Pinout
14 mm x 20 mm
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE#
Top View
VSS
CE#
A1
Notes:
1.
2.
3.
4.
5.
A1 is the least significant address bit.
A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).
A24 is valid for 256-Mbit densities; otherwise, it is a no connect (NC).
A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).
Please refer to the latest specification update for synchronous read operation with the TSOP package. The synchronous read
input signals (i.e. ADV# and CLK) should be tied off to support asynchronous reads. See Section 4.2, “Signal Descriptions”
on page 19.
Datasheet
16
November 2007
Order Number: 306666-11
NUMONYX [ NUMONYX B.V ]
