欢迎访问ic37.com |
会员登录 免费注册
发布采购

JS28F256P30T95 参数 Datasheet PDF下载

JS28F256P30T95图片预览
型号: JS28F256P30T95
PDF下载: 下载PDF文件 查看货源
内容描述: 恒忆的StrataFlash嵌入式存储器 [Numonyx StrataFlash Embedded Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 99 页 / 1401 K
品牌: NUMONYX [ NUMONYX B.V ]
 浏览型号JS28F256P30T95的Datasheet PDF文件第50页浏览型号JS28F256P30T95的Datasheet PDF文件第51页浏览型号JS28F256P30T95的Datasheet PDF文件第52页浏览型号JS28F256P30T95的Datasheet PDF文件第53页浏览型号JS28F256P30T95的Datasheet PDF文件第55页浏览型号JS28F256P30T95的Datasheet PDF文件第56页浏览型号JS28F256P30T95的Datasheet PDF文件第57页浏览型号JS28F256P30T95的Datasheet PDF文件第58页  
P30  
10.3.6  
Burst Sequence  
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst  
sequence is supported. Table 28 shows the synchronous burst sequence for all burst  
lengths, as well as the effect of the Burst Wrap (BW) setting.  
Table 28: Burst Sequence Word Ordering  
Burst Addressing Sequence (DEC)  
Start  
Addr.  
(DEC)  
Burst  
Wrap  
(RCR[3])  
4-Word Burst  
(BL[2:0] =  
0b001)  
8-Word Burst  
(BL[2:0] = 0b010)  
16-Word Burst  
(BL[2:0] = 0b011)  
Continuous Burst  
(BL[2:0] = 0b111)  
0
1
2
3
4
5
0
0
0
0
0
0
0-1-2-3  
1-2-3-0  
2-3-0-1  
3-0-1-2  
0-1-2-3-4-5-6-7  
1-2-3-4-5-6-7-0  
2-3-4-5-6-7-0-1  
3-4-5-6-7-0-1-2  
4-5-6-7-0-1-2-3  
5-6-7-0-1-2-3-4  
0-1-2-3-4…14-15  
1-2-3-4-5…15-0  
0-1-2-3-4-5-6-…  
1-2-3-4-5-6-7-…  
2-3-4-5-6-7-8-…  
3-4-5-6-7-8-9-…  
4-5-6-7-8-9-10…  
5-6-7-8-9-10-11…  
2-3-4-5-6…15-0-1  
3-4-5-6-7…15-0-1-2  
4-5-6-7-8…15-0-1-2-3  
5-6-7-8-9…15-0-1-2-3-4  
6-7-8-9-10…15-0-1-2-3-4-  
5
6
7
0
0
6-7-0-1-2-3-4-5  
7-0-1-2-3-4-5-6  
6-7-8-9-10-11-12-…  
7-8-9-10-11-12-13…  
7-8-9-10…15-0-1-2-3-4-5-  
6
14  
15  
0
0
14-15-0-1-2…12-13  
15-0-1-2-3…13-14  
14-15-16-17-18-19-20-…  
15-16-17-18-19-20-21-…  
0
1
2
3
4
5
6
1
1
1
1
1
1
1
0-1-2-3  
1-2-3-4  
2-3-4-5  
3-4-5-6  
0-1-2-3-4-5-6-7  
1-2-3-4-5-6-7-8  
0-1-2-3-4…14-15  
1-2-3-4-5…15-16  
2-3-4-5-6…16-17  
3-4-5-6-7…17-18  
4-5-6-7-8…18-19  
5-6-7-8-9…19-20  
6-7-8-9-10…20-21  
0-1-2-3-4-5-6-…  
1-2-3-4-5-6-7-…  
2-3-4-5-6-7-8-…  
3-4-5-6-7-8-9-…  
4-5-6-7-8-9-10…  
5-6-7-8-9-10-11…  
6-7-8-9-10-11-12-…  
2-3-4-5-6-7-8-9  
3-4-5-6-7-8-9-10  
4-5-6-7-8-9-10-11  
5-6-7-8-9-10-11-12  
6-7-8-9-10-11-12-13  
7-8-9-10-11-12-13-  
14  
7
1
7-8-9-10-11…21-22  
7-8-9-10-11-12-13…  
14  
15  
1
1
14-15-16-17-18…28-29  
15-16-17-18-19…29-30  
14-15-16-17-18-19-20-…  
15-16-17-18-19-20-21-…  
10.3.7  
Clock Edge  
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.  
This clock edge is used at the start of a burst cycle, to output synchronous data, and to  
assert/deassert WAIT.  
Datasheet  
54  
November 2007  
Order Number: 306666-11