P30
7.4
AC Write Specifications
Table 19: AC Write Specifications
Num
W1
Symbol
tPHWL
Parameter
Min
Max
Unit
Notes
RST# high recovery to WE# low
CE# setup to WE# low
150
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,3
1,2,4
W2
tELWL
0
W3
tWLWH
tDVWH
tAVWH
tWHEH
tWHDX
tWHAX
tWHWL
tVPWH
tQVVL
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
50
W4
50
W5
50
W6
0
1,2
W7
0
W8
0
W9
20
1,2,5
W10
W11
W12
W13
W14
W16
VPP setup to WE# high
200
1,2,3,7
1,2,3,7
VPP hold from Status read
WP# hold from Status read
WP# setup to WE# high
WE# high to OE# low
0
tQVBL
0
200
tBHWH
tWHGL
tWHQV
0
1,2,9
WE# high to read valid
tAVQV + 35
1,2,3,6,10
Write to Asynchronous Read Specifications
W18 tWHAV WE# high to Address valid
Write to Synchronous Read Specifications
0
-
ns
1,2,3,6,8
W19
W20
tWHCH/L
tWHVH
WE# high to Clock valid
WE# high to ADV# high
19
19
-
-
ns
ns
1,2,3,6,10
Write Specifications with Clock Active
W21
W22
tVHWL
tCHWL
ADV# high to WE# low
Clock high to WE# low
-
-
20
20
ns
ns
1,2,3,11
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH
.
5.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).
6.
7.
8.
tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read.
VPP and WP# should be at a valid level until erase or program success is determined.
This specification is only applicable when transitioning from a write cycle to an asynchronous read. See spec W19 and
W20 for synchronous read.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
Add 10 ns if the write operation results in a RCR or block lock status change, for the subsequent read operation to reflect
this change.
9.
10.
11.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
Datasheet
36
November 2007
Order Number: 306666-11
NUMONYX [ NUMONYX B.V ]
