P30
Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
R108
R111
tAPA
tphvh
Page address access
-
25
-
ns
ns
1
RST# high to ADV# high
30
Clock Specifications
-
-
52
40
-
MHz
MHz
ns
R200
R201
fCLK
CLK frequency
CLK period
TSOP
TSOP
19.2
25
5
tCLK
1,3,5,6
-
ns
R202
R203
tCH/CL
CLK high/low time
CLK fall/rise time
-
ns
tFCLK/RCLK
-
3
ns
Synchronous Specifications(5,6)
R301
R302
R303
R304
R305
R306
R307
R311
R312
tAVCH/L
tVLCH/L
tELCH/L
tCHQV / tCLQV
tCHQX
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
9
9
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
9
-
-
17
-
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
3
1,7
1,4,7
1,7
1
tCHAX
10
-
-
tCHTV
17
-
tCHVL
CLK Valid to ADV# Setup
WAIT Hold from CLK
3
tCHTX
3
-
1,7
Notes:
1.
See Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max
allowable input slew rate.
2.
3.
4.
5.
6.
7.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
Sampled, not 100% tested.
Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package.
Synchronous read mode is not supported with TTL level inputs.
Applies only to subsequent synchronous reads.
Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 1 of 3)
Num
Symbol
Parameter
Speed
Min
Max
Unit
Notes
Asynchronous Specifications
VCC = 1.8 V – 2.0
85
88
95
-
-
-
V
VCC = 1.7 V – 2.0
V
R1
R2
tAVAV
Read cycle time
ns
256/512-Mb TSOP
packages
VCC = 1.8 V – 2.0
V
85
88
95
VCC = 1.7 V – 2.0
V
tAVQV
Address to output valid
-
ns
256/512-Mb TSOP
packages
-
Datasheet
30
November 2007
Order Number: 306666-11
NUMONYX [ NUMONYX B.V ]
