Intel® Embedded Flash Memory (J3 v. D)
1.0
Introduction
This document contains information pertaining to the Intel® Embedded Flash Memory
(J3 v. D) device features, operation, and specifications.
The Intel® Embedded Flash Memory J3 Version D (J3 v. D) provides improved
mainstream performance with enhanced security features, taking advantage of the
high quality and reliability of the NOR-based Intel 0.13 µm ETOX™ VIII process
technology. Offered in 256-Mbit, 128-Mbit, 64-Mbit, and 32-Mbit densities, theIntel®
Embedded Flash Memory (J3 v. D)device brings reliable, low-voltage capability (3 V
read, program, and erase) with high speed, low-power operation. The Intel® Embedded
Flash Memory (J3 v. D) device takes advantage of proven manufacturing experience
and is ideal for code and data applications where high density and low cost are
required, such as in networking, telecommunications, digital set top boxes, audio
recording, and digital imaging.Intel® Flash Memory components also deliver a new
generation of forward-compatible software support. By using the Common Flash
Interface (CFI) and Scalable Command Set (SCS), customers can take advantage of
density upgrades and optimized write capabilities of future Intel® Flash Memory
devices.
The J3v.D product family is also planned on the Intel 65nm process lithography, 65nm
AC timing changes are noted in this datasheet and should be taken into account for all
new designs.
1.1
Nomenclature
All Densities
All Densities
32 Mbit
AMIN = A0 for x8
AMIN = A1 for x16
AMAX = A21
AMIN
AMAX
64 Mbit
AMAX = A22
128 Mbit
256 Mbit
AMAX = A23
AMAX = A24
Block
Clear
Program
Set
A group of flash cells that share common erase circuitry and erase simultaneously.
Indicates a logic zero (0)
Writes data to the flash array
Indicates a logic one (1)
VPEN
VPEN
Refers to a signal or package connection name
Refers to timing or voltage levels
1.2
Acronyms
CUI
OTP
PLR
Command User Interface
One Time Programmable
Protection Lock Register
Datasheet
6
December 2007
Document Number: 316577-006